Currently available hybrid pixel detectors are constructed by bonding custom Application Specific Integrated Circuits (ASICs) to a relatively small sensor slab. Coverage of a larger area is then obtained by tiling or shingling together some number of modules, which leads to gaps in coverage along the module boundaries.
The architecture of existing pixel front-end circuitry for large dynamic range is typically an adaptive-gain active integrator, which is a high gain amplifier with switchable capacitors in the feedback loop. Different capacitors are switched in on-the-fly during integration, depending on the signal amplitude. To achieve large dynamic range with this scheme, the total integration capacitance must be large, which forces either large pixel size or limited dynamic range. In addition, an image of the signal charge must be actively sourced with high bandwidth by the amplifier and power supply, requiring relatively large bias currents and unacceptably high power dissipation.
Therefore, there is a need in the art for new methods, systems, and apparatuses for wafer-scale gapless and seamless detectors with small pixels, which have both high dynamic range and low power dissipation.